1. Field of the Invention
The present invention relates to a color liquid crystal display control system suitable for a laptop computer having a color liquid crystal display.
2. Description of the Related Art
As a conventional display monitor of a laptop computer, a flat-panel display such as a liquid crystal display (LCD) is used. A color CRT monitor can be connected to a laptop computer as an option. An arrangement of a color liquid crystal display control system in a laptop computer which has a color LCD as standard equipment and to which a color CRT display is connected as an option is shown in FIG. 1. In FIG. 1, a system bus 1 is constituted by an address bus having a 16-bit width and a data bus having a 16-bit width. Transfer of address and data is performed between a CPU 3 and each memory through the system bus 1. A video RAM (VRAM) 5 stores color display data displayed on a color CRT display 7 and a color LCD (liquid crystal display) 9. The VRAM 5 has a memory capacity of 64K.times.16 bits. The CPU 3 writes the display data in the VRAM 5 through a CRT controller 11 in response to a write command. The CRT controller 11 outputs the display data read out from the VRAM 5 to a display controller 15 and a display data generator (DAC) 17 through a display data bus 13 having a 8-bit width. The display data generator 17 converts the display data output from the CRT controller 11 into R, G, and B display data to output them to the color CRT display 7. A CRT palette 19 and a digital/analog convertor (not shown) are incorporated in the DAC 17. The color CRT display 7 is a display which can perform multi-color (256 colors of 256K (=262,144) colors) display at a high resolution (720.times.480 dots). The color CRT display 7 is synchronized with a horizontal sync signal (HSYNC) output from the CRT controller 11 and a vertical sync signal (VSYNC) 21 to display 18-bit RGB color display data from the analog output port of the DAC 17. The CRT palette 19 converts the display data output from the CRT controller 11 in designated colors. The display data converted by the CRT palette 19 in the designated colors is converted into R, G, and B analog display data by the DAC 17 to be output to the CRT display 7. The CRT display 7 displays a color image on the basis of the colors designated by the CRT palette 19. The display controller (DC) 15 is constituted by a gate array on which various functional circuits for controlling the display of the color LCD 9 and a bus interface function of transferring various display control data between the CPU 3 and the display controller 15 through the system bus 1 are mounted. In the arrangement shown in FIG. 1, when the palette data from the CRT palette 19 is updated, an arithmetic and logic section 23 calculates a gray-scale parameter having 39 gray scale levels from the data in accordance with a predetermined arithmetic expression. In addition, the arrangement includes a conversion table 25 for converting the 39-gray-scale parameter output from the arithmetic and logic section 23 into data having 16 gray scale levels and an LCD palette 27 in which the grayscale data generated from the conversion table 25 is set. The LCD palette 27 converts the display data output from the CRT controller 11 through the display data bus 13 into 4-bit R, G, B, and I data through the arithmetic and logic section 23 and conversion table 25 in the DC 15. The detailed description of the operation of the arithmetic and logic section 23 and conversion table 25 is disclosed in U.S. patent application Ser. No. 406,066 filed by the same assignee as that of the present invention. At this time, the LCD palette 27 is updated in accordance with updating of the CRT palette 19. The color LCD 9 is a color display capable of performing 16-color display. The color LCD 9 is synchronized with HSYNC and VSYNC signals 21 output from the CRT controller 11 to output 4-bit R, G, B, and I color display data from the digital port of the DC 15. A data bus 29 is a 16-bit bus for transferring various data including update palette data between the system bus 1 and the DC 15. A data bus 31 is a bus used for writing color designation data on the CRT palette 19 in the DAC 17. Each of address buses 33 and 35 is constituted by a bus having a 16-bit width. An address value from the CPU is input to the DC 15 and the CRT controller 11. The internal bus 37 is a bidirectional bus which transfers write data to the VRAM 5 and its address value between the DC 15 and the CRT controller 11. An address value designated by the CPU 3 through an address bus 39 having an 8-bit width is designated to the VRAM 5 by the CRT controller 11, and the CRT controller 11 reads out display data from VRAM 5 at a read timing.
The CRT display data sent from the CRT controller 11 to the DAC 17 is converted into 4-bit R, G, B, and I color data using the LCD palette 27 of the DC 15. For this reason, the number of colors displayed on the color LCD 9 is limited to the number of gray scales of the LCD palette 27. Therefore, when an application program made for, e.g., a color CRT is executed using the color LCD, it is desired that the designated 256 colors or less are further faithfully reproduced by the color LCD.